3 results match your criteria: "Nokia Research Centre Cambridge[Affiliation]"
Polyaniline (PANI) nanobrushes were synthesized by template-free electrochemical galvanostatic methods. When the same method was applied to the carbon nanohorn (CNH) solution containing aniline monomers, a hybrid nanostructure containing PANI and CNHs was enabled after electropolymerization. This is the first report on the template-free method to make PANI nanobrushes and homogeneous hybrid soft matter (PANI) with carbon nanoparticles.
View Article and Find Full Text PDFACS Nano
June 2009
Nokia Research Centre Cambridge U.K., c/o Nanoscience Centre, University of Cambridge, Cambridge, United Kingdom.
Top-gated silicon nanowire transistors are fabricated by preparing all terminals (source, drain, and gate) on top of the nanowire in a single step via dose-modulated e-beam lithography. This outperforms other time-consuming approaches requiring alignment of multiple patterns, where alignment tolerances impose a limit on device scaling. We use as gate dielectric the 10-15 nm SiO(2) shell naturally formed during vapor-transport growth of Si nanowires, so the wires can be implemented into devices after synthesis without additional processing.
View Article and Find Full Text PDFNano Lett
May 2008
Nokia Research Centre Cambridge U.K., c/o Nanoscience Centre, Cambridge CB3 0FF, UK.
Nanowire lithography (NWL) uses nanowires (NWs), grown and assembled by chemical methods, as etch masks to transfer their one-dimensional morphology to an underlying substrate. Here, we show that SiO2 NWs are a simple and compatible system to implement NWL on crystalline silicon and fabricate a wide range of architectures and devices. Planar field-effect transistors made of a single SOI-NW channel exhibit a contact resistance below 20 kOmega and scale with the channel width.
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