High-Breakdown and Low-Leakage 4H-SiC MOS Capacitor Based on HfO/SiO Stacked Gate Dielectric in Trench Structures.

The progression of SiC MOSFET technology from planar to trench structures requires optimized gate oxide layers within the trench to enhance device performance. In this study, we investigated the interface characteristics of HfO and SiO/HfO gate dielectrics grown by atomic layer deposition (ALD) on SiC trench structures. The trench structure morphology was revealed using scanning electron microscopy (SEM). Atomic force microscopy (AFM) measurements showed that the roughness of both films was below 1nm. Spectroscopic ellipsometry (SE) indicated that the physical thicknesses of HfO and SiO/HfO were 38.275 nm and 40.51 nm, respectively, demonstrating their comparable thicknesses. X-ray photoelectron spectroscopy (XPS) analysis of the gate dielectrics revealed almost identical Hf 4f core levels for both HfO and the SiO/HfO composite dielectrics, suggesting that the SiO interlayer and the SiC substrate had minimal impact on the electronic structure of the HfO film. The breakdown electric field of the HfO film was recorded as 4.1 MV/cm, with a leakage current at breakdown of 1.1 × 10A/cm. The SiO/HfO stacked film exhibited significantly better performance, with a breakdown electric field of 6.5 MV/cm and a marked reduction in leakage current to 3.7 × 10 A/cm. A detailed extraction and analysis of the leakage current mechanisms were proposed, and the data suggested that the introduction of thin SiO interfacial layers effectively mitigated small bandgap offset issues, significantly reducing leakage current and improving device performance.