The chemical-mechanical polishing (CMP) of silicon wafers involves high-precision surface machining after double-sided lapping. Silicon wafers are subjected to chemical corrosion and mechanical removal under pressurized conditions. The multichip CMP process for 4~6-inch silicon wafers, such as those in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), and MEMS (Micro-Electromechanical System) field materials, is conducted to maintain multiple chips to improve efficiency and improve polish removal uniformity; that is, the detected TTV (total thickness variation) gradually increases from 10 μm to less than 3 μm. In this work, first, a mathematical model for calculating the small deflection of silicon wafers under pressure is established, and the limit values under two boundary conditions of fixed support and simple support are calculated. Moreover, the removal uniformity of the silicon wafers is improved by improving the uniformity of the wax-coated adhesion state and adjusting the boundary conditions to reflect a fixed support state. Then, the stress distribution of the silicon wafers under pressure is simulated, and the calculation methods for measuring the TTV of the silicon wafers and the uniformity measurement index are described. Stress distribution is changed by changing the size of the pressure ring to achieve the purpose of removing uniformity. This study provides a reference for improving the removal uniformity of multichip silicon wafer chemical-mechanical polishing.
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| http://www.ncbi.nlm.nih.gov/pmc/articles/PMC11857252 | PMC |
| http://dx.doi.org/10.3390/mi16020198 | DOI Listing |
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