The practicality of memristor-based computation-in-memory (CIM) systems is limited by the specific hardware design and the manual parameters tuning process. Here, we introduce a software-hardware co-development approach to improve the flexibility and efficiency of the CIM system. The hardware component supports flexible dataflow, and facilitates various weight and input mappings. The software aspect enables automatic model placement and multiple efficient optimizations. The proposed optimization methods can enhance the robustness of model weights against hardware nonidealities during the training phase and automatically identify the optimal hardware parameters to suppress the impacts of analogue computing noise during the inference phase. Utilizing the full-stack system, we experimentally demonstrate six neural network models across four distinct tasks on the hardware automatically. With the help of optimization methods, we observe a 4.76% accuracy improvement for ResNet-32 during the training phase, and a 3.32% to 9.45% improvement across the six models during the on-chip inference phase.
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http://dx.doi.org/10.1038/s41467-025-57183-0 | DOI Listing |
Nat Commun
March 2025
School of Integrated Circuits, Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing, China.
The practicality of memristor-based computation-in-memory (CIM) systems is limited by the specific hardware design and the manual parameters tuning process. Here, we introduce a software-hardware co-development approach to improve the flexibility and efficiency of the CIM system. The hardware component supports flexible dataflow, and facilitates various weight and input mappings.
View Article and Find Full Text PDFNat Comput Sci
January 2025
School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing, China.
Labeling data is a time-consuming, labor-intensive and costly procedure for many artificial intelligence tasks. Deep Bayesian active learning (DBAL) boosts labeling efficiency exponentially, substantially reducing costs. However, DBAL demands high-bandwidth data transfer and probabilistic computing, posing great challenges for conventional deterministic hardware.
View Article and Find Full Text PDFFront Neurosci
December 2021
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China.
In this work, a memristive spike-based computing in memory (CIM) system with adaptive neuron (MSPAN) is proposed to realize energy-efficient remote arrhythmia detection with high accuracy in edge devices by software and hardware co-design. A multi-layer deep integrative spiking neural network (DiSNN) is first designed with an accuracy of 93.6% in 4-class ECG classification tasks.
View Article and Find Full Text PDFFundam Res
January 2022
School of Integrated Circuits (SIC), Beijing Innovation Center for Future Chips (ICFC), Tsinghua University, Beijing, China.
Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis. These data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units (CPUs) and graphics processing units (GPUs). Computation-in-memory (CIM) provides a possible solution for highly efficient morphology operations.
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