Despite being a high-resolution separation technique, deterministic lateral displacement (DLD) technology is facing multiple challenges with regard to design, manufacture, and operation of pertinent devices. This work specifically aims at alleviating difficulties associated with design and manufacture of DLD chips. The process of design and production of computer-aided design (CAD) mask layout files that are typically required for computational modeling analysis, optimization, as well as for manufacturing DLD-based micro/nanofluidic chips is complex, time-consuming, and often necessitates a high level of expertise in the field. Herein, we report a universal framework to automate the process of designing DLD and producing layout CAD files for various systems spanning from simply a single DLD unit to complex parallelized DLD structures with/without additional upstream/downstream components, , inlet filter, preload, collection channels, and through-wafer vias. In addition, to the best of our knowledge, for the first time, we adopt imprint lithography (IL) into fabrication process flow to define fine features of parallelized DLD arrays, while avoiding problems in connection with accessibility and cost of advanced photolithography tools. With regard to parallelized DLD architectures, we also report a new fabrication process flow aiming at mitigating the problems related to creating through-silicon vias at high yield. We demonstrate some use cases of our developed design and manufacture framework by designing and fabricating multiple devices to separate microspheres (0.6 μm and 1.3 μm) from aqueous media. We believe that our design automation package offers a user-friendly workflow, significantly alleviating the hurdles associated with design and optimization of DLD structures, while our fabrication process flow can provide an accessible solution to manufacturing micron- and submicron-scale DLD chips. These innovations should enable a larger community to adopt the DLD technology into their research, particularly for lab-on-a-chip applications.

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http://dx.doi.org/10.1039/d4lc00838cDOI Listing

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