An innovative GaN trench MOSFET featuring an ultra-low gate-drain charge (Q) is proposed, with its operational mechanisms thoroughly investigated using TCAD simulations. This novel MOSFET design introduces a triple-shield structure (BPSG-MOS) comprising three critical components: (1) a grounded split gate (SG), (2) a P+ shield region (PSR), and (3) a semi-wrapped BP layer that extends the P-shield beneath the gate and along the sidewalls of the trench gate. Both the SG and PSR effectively reduce gate-drain coupling, transforming most of the gate-drain capacitance (C) into a series combination of gate-source capacitance (C) and drain-source capacitance (C). Furthermore, the BP layer refines the gate-drain capacitance by converting the C at the trench gate sidewalls into C. This configuration significantly lowers C, resulting in an ultra-low Q. Compared to the dual-shield MOSFET (PSGT-MOS) and the conventional trench MOSFET (TG-MOS), the BPSG-MOS achieves reductions in C by 81% and 98%, respectively.
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http://dx.doi.org/10.1038/s41598-024-84007-w | DOI Listing |
Sci Rep
January 2025
College of Physics and Electronic Information, Baicheng Normal University, Jilin, 137000, China.
An innovative GaN trench MOSFET featuring an ultra-low gate-drain charge (Q) is proposed, with its operational mechanisms thoroughly investigated using TCAD simulations. This novel MOSFET design introduces a triple-shield structure (BPSG-MOS) comprising three critical components: (1) a grounded split gate (SG), (2) a P+ shield region (PSR), and (3) a semi-wrapped BP layer that extends the P-shield beneath the gate and along the sidewalls of the trench gate. Both the SG and PSR effectively reduce gate-drain coupling, transforming most of the gate-drain capacitance (C) into a series combination of gate-source capacitance (C) and drain-source capacitance (C).
View Article and Find Full Text PDFMicromachines (Basel)
July 2024
Department of Electrical Engineering, Xi'an University of Technology, Xi'an 710048, China.
A silicon carbide (SiC) SGT MOSFET featuring a ""-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts.
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June 2024
State Key Laboratory of Wide-Bandgap Semiconductor Devices and Integrated Technology, School of Microelectronics, Xidian University, Xi'an 710071, China.
This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical-thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide.
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May 2024
School of Electrical Engineering, Southwest Jiaotong University, Chengdu 611756, China.
In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region.
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May 2024
School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, China.
In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance.
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