Semiconductor photodetectors integrating preliminary signal-processing functions play a vital role in artificial biomimetic retina systems. Herein, we propose a tungsten diselenide (WSe) phototransistor with a dual-layer gate dielectric and an asymmetric graphene insert structure. This phototransistor exhibits a bidirectional self-powered photocurrent by controlling the gate voltage via the formation of reconfigurable p-p and n-p homojunctions in the channel from the asymmetric graphene insert. At the same time, the nonvolatile electron and hole stored in the dual-layer gate dielectric are generated using a temporary gate voltage, which can replace the gate voltage to regulate the channel charge. Moreover, the photocurrent shows a linear relation with the temporary programming gate voltage. The phototransistor exhibits a rectification ratio of >4 orders of magnitude without the gate voltage, indicating its significant capability to operate in a fully self-powered mode with near-zero power consumption. Based on the device characteristics, we successfully simulate the biological functions of the photoreceptor layer and bipolar cell layer in the retinal receptive field. The identification of the object motion direction in the receptive field can be realized by integrating three programmable devices on the chip. Furthermore, edge enhancement of the image is achieved by independently modulating the light response of each pixel in the sensor by varying the programming gate voltage. This study will promote the developing progress of future artificial biomimetic retina systems.
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http://dx.doi.org/10.1021/acsnano.4c10619 | DOI Listing |
ACS Nano
December 2024
MIIT Key Laboratory of Advanced Display Materials and Devices, Jiangsu Engineering Research Center for Quantum Dot Display, School of Materials Science and Engineering, Institute of Optoelectronics & Nanomaterials, Nanjing University of Science and Technology, Nanjing, Jiangsu 210094, China.
Reconfigurable field-effect transistors (RFETs) offer notable benefits on electronic and optoelectronic logic circuits, surpassing the integration, flexibility, and cost-efficiency of conventional complementary metal-oxide semiconductor transistors. The low on/off current ratio of these transistors remains a considerable impediment in the practical application of RFETs. To overcome these limitations, a van der Waals heterojunction (vdWH) transistor composed of WSe/TaNiSe has been proposed.
View Article and Find Full Text PDFACS Meas Sci Au
December 2024
Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave. SE, Minneapolis 55455, Minnesota, United States.
The diversification of electronic materials in devices provides a strong incentive for methods to rapidly correlate device performance with fabrication decisions. In this work, we present a low-cost automated test station for gated electronic transport measurements of field-effect transistors. Utilizing open-source PyMeasure libraries for transparent instrument control, the "ATLAS-MAP" system serves as a customizable interface between sourcemeters and samples under test and is programmed to conduct transfer curve and van der Pauw methods with static and sweeping gate voltages.
View Article and Find Full Text PDFNano Lett
December 2024
Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576.
Targeting high-performance computing at cryogenic temperatures, we report back-end-of-line (BEOL)-compatible p-type Te-TeO field effect transistors (FETs) deposited using a sputtering method that is cost-effective, large-scale manufacturable, and highly controllable. Combined with the indium tin oxide channel n-FETs employing a common gate and HfO gate dielectric, BEOL three-dimensional stackable oxide semiconductor complementary metal oxide semiconductor (CMOS) inverters were further realized, demonstrating excellent threshold voltage matching, with a high voltage gain of 132 with a 2 V supply voltage () at room temperature. At cryogenic temperatures, the CMOS inverter exhibits significantly enhanced performance, achieving a voltage gain of 233 at a of 2 V with a wide noise margin of 86%.
View Article and Find Full Text PDFNanoscale
December 2024
Layered Materials and Device Physics Laboratory, Department of Chemistry, Physics and Atmospheric Science, Jackson State University, Jackson, MS 39217, USA.
The metal-to-insulator phase transition (MIT) in two-dimensional (2D) materials under the influence of a gating electric field has revealed interesting electronic behavior and the need for a deeper fundamental understanding of electron transport processes, while attracting much interest in the development of next-generation electronic and optoelectronic devices. Although the mechanism of the MIT in 2D semiconductors is a topic under debate in condensed matter physics, our work demonstrates the tunable percolative phase transition in few-layered MoSe field-effect transistors (FETs) using different metallic contact materials. Here, we attempted to understand the MIT through temperature-dependent electronic transport measurements by tuning the carrier density in a MoSe channel under the influence of an applied gate voltage.
View Article and Find Full Text PDFACS Appl Mater Interfaces
December 2024
Department of Materials Science and Engineering, National Cheng Kung University, Tainan 70101, Taiwan.
Components needed in Artificial Intelligence with a higher information capacity are critically needed and have garnered significant attention at the forefront of information technology. This study utilizes solution-processed zinc-tin oxide (ZTO) thin-film phototransistors and modulates the values of , which allows for the regulation of electron trapping/detrapping at the ZTO/SiO interface. By coupling the excited photonic carrier and electronic trapping, logic gates such as "AND," "OR," "NAND," and "NOR" can be achieved.
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