Wafer-scale aligned carbon nanotubes (A-CNTs) are promising candidate semiconductors for building high-performance complementary metal-oxide-semiconductor (CMOS) transistors for future integrated circuits (ICs). A-CNT-based p-type field-effect transistors (P-FETs) have demonstrated excellent performance and scalability down to sub-10 nm nodes. However, the development of A-CNT n-type FETs (N-FETs) lags far behind, in regard to their electronic performance and device scaling. In this work, we fabricated top-gated N-FETs based on A-CNTs with a scandium (Sc)-contacted source and drain. High-performance A-CNT N-FETs were demonstrated with record on-state current () exceeding 1 mA/μm and peak transconductance () of 0.4 mS/μm. Interestingly, the A-CNT N-FETs exhibited abnormal scaling behavior owing to the lateral oxidation of low-work function source/drain contacts, leading to formidable challenges to scale both the gate length () and the contact length () at the same time. Understanding of the abnormal scaling behavior contributes to seeking solutions for high-performance A-CNT N-FETs, and it paves the way for future CNT CMOS digital IC technology.
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http://dx.doi.org/10.1021/acsami.4c11320 | DOI Listing |
ACS Appl Mater Interfaces
October 2024
Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China.
ACS Nano
December 2022
Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China.
High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide-semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs).
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