The contact resistance formed between MoS and metal electrodes plays a key role in MoS-based electronic devices. The Schottky barrier height (SBH) is a crucial parameter for determining the contact resistance. However, the SBH is difficult to modulate because of the strong Fermi-level pinning (FLP) at MoS-metal interfaces. Here, we investigate the FLP effect and the contact types of monolayer and multilayer MoS-metal van der Waals (vdW) interfaces using density functional theory (DFT) calculations based on Perdew-Burke-Ernzerhof (PBE) level. It has been demonstrated that, compared with monolayer MoS-metal close interfaces, the FLP effect can be significantly reduced in monolayer MoS-metal vdW interfaces. Furthermore, as the layer number of MoS increases from 1L to 4L, the FLP effect is first weakened and then increased, which can be attributed to the charge redistribution at the MoS-metal and MoS-MoS interfaces. In addition, the p-type Schottky contact can be achieved in 1L-4L MoS-Pt, 3L MoS-Au, and 2L-3L MoS-Pd vdW interfaces, which is useful for realizing complementary metal oxide semiconductor (CMOS) logic circuits. These findings indicated that the FLP and contact types can be effectively modulated at MoS-metal vdW interfaces by selecting the layer number of MoS.
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http://dx.doi.org/10.3390/nano14131075 | DOI Listing |
ACS Nano
December 2024
Department of Materials Science and Engineering, Hanbat National University, Daejeon 34158, Republic of Korea.
Ultrasmall-scale semiconductor devices (≤5 nm) are advancing technologies, such as artificial intelligence and the Internet of Things. However, the further scaling of these devices poses critical challenges, such as interface properties and oxide quality, particularly at the high-/semiconductor interface in metal-oxide-semiconductor (MOS) devices. Existing interlayer (IL) methods, typically exceeding 1 nm thickness, are unsuitable for ultrasmall-scale devices.
View Article and Find Full Text PDFACS Appl Mater Interfaces
December 2024
Beijing Academy of Quantum Information Sciences, Beijing 100193, China.
Two-dimensional van der Waals (vdW) layered materials not only are an intriguing fundamental scientific research platform but also provide various applications to multifunctional quantum devices in the field-effect transistors (FET) thanks to their excellent physical properties. However, a metal-semiconductor (MS) interface with a large Schottky barrier causes serious problems for unleashing their intrinsic potentials toward the advancements in high-performance devices. Here, we show that exfoliated vdW Dirac semimetallic PtTe can be an excellent electrode for electrons in MoS FETs.
View Article and Find Full Text PDFACS Nano
December 2024
Department of Physics, Yonsei University, Seoul 03722, Republic of Korea.
To achieve the commercialization of two-dimensional (2D) semiconductors, the identification of an appropriate combination of 2D semiconductors and three-dimensional (3D) metals is crucial. Furthermore, understanding the van der Waals (vdW) interactions between these materials in thin-film semiconductor processes is essential. Optimizing these interactions requires precise control over the properties of the vdW interface through specific pre- or post-treatment methods.
View Article and Find Full Text PDFAdv Mater
December 2024
Institute of Materials Research, Center of Double Helix, Guangdong Provincial Key Laboratory of Thermal Management Engineering and Materials, Shenzhen Key Laboratory of Advanced Layered Materials for Value-added Applications, Institute of Materials Research, Tsinghua Shenzhen International Graduate School, Tsinghua University, Shenzhen, 518055, P. R. China.
Liquid exfoliation is a scalable and effective method for synthesizing 2D nanosheets (NSs) but often induces contamination and defects. Here, liquid metal gallium (Ga) is used to exfoliate bulk layered materials into 2D NSs at near room temperature, utilizing the liquid surface tension and Ga intercalation to disrupt Van der Waals (vdW) forces. In addition, the process can transform the 2H-phase of transition metal dichalcogenides into the 1T'-phase under ambient conditions.
View Article and Find Full Text PDFAdv Mater
December 2024
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, 78712, USA.
A synaptic memristor using 2D ferroelectric junctions is a promising candidate for future neuromorphic computing with ultra-low power consumption, parallel computing, and adaptive scalable computing technologies. However, its utilization is restricted due to the limited operational voltage memory window and low on/off current (I) ratio of the memristor devices. Here, it is demonstrated that synaptic operations of 2D InSe ferroelectric junctions in a planar memristor architecture can reach a voltage memory window as high as 16 V (±8 V) and I ratio of 10, significantly higher than the current literature values.
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