Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 μW and 53 μW, and an energy per pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy per pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.

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http://dx.doi.org/10.1109/TBCAS.2024.3422282DOI Listing

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