Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (W) and the neighboring gate oxide width (t) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell-Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO, SiN, AlO, HfO, LaO, and TiO perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (I) reduced down to 6.45 × 10 A for the AlO: TiO combination and a gate leakage current (I) reaching down to 2.04 × 10 A for the AlO: HfO: LaO combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.