Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.
Download full-text PDF |
Source |
|---|---|
| http://dx.doi.org/10.1021/acsami.4c03785 | DOI Listing |
Publication Analysis
Top Keywords
Similar Publications
All Light Controlled Five State Logic Gates on a Ferroelectric Ceramic Chip.
Adv Mater
January 2025
State Key Laboratory of High-Performance Ceramics and Superfine Microstructure, Shanghai Institute of Ceramics, Chinese Academy of Sciences, Shanghai, 200050, China.
Differentiating photoelectric response in a single material with a simple approach is desirable for all-in-one optoelectronic logical devices. In ferroelectric materials, significantly distinct photoelectric features should be observed if they are in diverse polarization states, unveiling a possible pathway to realize multifunctional optoelectronic logic gates through ferroelectric polarization design. In this study, the Ti self-doping strategy is first applied to 0.
View Article and Find Full Text PDFLow-power edge detection based on ferroelectric field-effect transistor.
Nat Commun
January 2025
Hangzhou Institute of Technology, Xidian University, Hangzhou, 311231, China.
Edge detection is one of the most essential research hotspots in computer vision and has a wide variety of applications, such as image segmentation, target detection, and other high-level image processing technologies. However, efficient edge detection is difficult in a resource-constrained environment, especially edge-computing hardware. Here, we report a low-power edge detection hardware system based on HfO-based ferroelectric field-effect transistor, which is one of the most potential non-volatile memories for energy-efficient computing.
View Article and Find Full Text PDFHafnia-Based Ferroelectric Transistor with Poly-Si Gates for Gate-First Three-Dimensional NAND Structures.
ACS Appl Mater Interfaces
December 2024
Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea.
Ferroelectric transistors based on hafnia-based ferroelectrics have emerged as promising candidates for next-generation memory devices. Additionally, hafnia-based ferroelectric transistors are suggested for three-dimensional (3D) memory devices, such as 3D ferroelectric NAND. This paper investigates the utilization of poly-Si as a gate material for hafnia-based ferroelectric transistors in 3D NAND structures.
View Article and Find Full Text PDFExploring Disturb Characteristics in 2D and 3D Ferroelectric NAND Memory Arrays for Next-Generation Memory Technology.
ACS Appl Mater Interfaces
July 2024
Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Korea.
Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array.
View Article and Find Full Text PDFHafnia-Based Ferroelectric Memory: Device Physics Strongly Correlated with Materials Chemistry.
J Phys Chem Lett
February 2024
Department of Materials Science and Engineering & Inter-University Semiconductor Research Center, College of Engineering, Seoul National University, Gwanak-ro 1, Gwanak-gu, Seoul 08826, Republic of Korea.
Hafnia-based ferroelectrics and their semiconductor applications are reviewed, focusing on next-generation dynamic random-access-memory (DRAM) and Flash. The challenges of achieving high endurance and high write/read speed and the optimal material properties to achieve them are discussed. In DRAM applications, the trade-off between remanent polarization (), endurance, and operation speed is highlighted, focusing on reducing the critical material property (coercive field).
View Article and Find Full Text PDFWant AI Summaries of new PubMed Abstracts delivered to your In-box?
Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!