For several decades after Moore's Law is proposed, there is a continuous effort to reduce the feature-size of transistors. However, as the size of transistors continues to decrease, numerous challenges and obstacles including severe short channel effects (SCEs) are emerging. Recently, low-dimensional materials have provided new opportunities for constructing small feature-size transistors due to their superior electrical properties compared to silicon. Here, state-of-the-art low-dimensional materials-based transistors with small feature-sizes are reviewed. Different from other works that mainly focus on material characteristics of a specific device structure, the discussed topics are utilizing device structure design including vertical structure and nano-gate structure, and nanofabrication techniques to achieve small feature-sizes of transistors. A comprehensive summary of these small feature-size transistors is presented by illustrating their operation mechanism, relevant fabrication processes, and corresponding performance parameters. Besides, the role of small feature-size transistors based on low-dimensional materials in further reducing the small footprint is also clarified and their cutting-edge applications are highlighted. Finally, a comparison and analysis between state-of-art transistors is made, as well as a glimpse into the future research trajectory of low dimensional materials-based small feature-size transistors is briefly outlined.
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http://dx.doi.org/10.1002/advs.202400500 | DOI Listing |
Nat Commun
December 2024
Department of Materials Science and NanoEngineering and the Rice Advanced Materials Institute, Rice University, Houston, TX, 77005, USA.
As the feature size of microelectronic circuits is scaling down to nanometer order, the increasing interconnect crosstalk, resistance-capacitance (RC) delay and power consumption can limit the chip performance and reliability. To address these challenges, new low-k dielectric (k < 2) materials need to be developed to replace current silicon dioxide (k = 3.9) or SiCOH, etc.
View Article and Find Full Text PDFMater Horiz
November 2024
School of Materials Science and Engineering, State Key Laboratory of Structural Analysis, Optimization and CAE Software for Industrial Equipment, National Engineering Research Center for Advanced Polymer Processing Technology Zhengzhou University, Zhengzhou 450001, China.
High dielectric constant () polymers have been widely explored for flexible, low-power-consumption electronic devices. In this work, solution-processable high- polymers were designed and synthesized by ultraviolet (UV) triggered crosslinking at a low temperature (60 °C). The highly crosslinked network allows for high resistance to organic solvents and high breakdown strength over 2 MV cm.
View Article and Find Full Text PDFACS Nano
August 2024
State Key Laboratory of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China.
The silicon nanowire field-effect transistor (SiNW FET) has been developed for over two decades as an ultrasensitive, label-free biosensor for biodetection. However, inconsistencies in manufacturing and surface functionalization at the nanoscale have led to poor sensor-to-sensor consistency in performance. Despite extensive efforts to address this issue through process improvements and calibration methods, the outcomes have not been satisfactory.
View Article and Find Full Text PDFAdv Sci (Weinh)
September 2024
School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing, 100081, P. R. China.
For several decades after Moore's Law is proposed, there is a continuous effort to reduce the feature-size of transistors. However, as the size of transistors continues to decrease, numerous challenges and obstacles including severe short channel effects (SCEs) are emerging. Recently, low-dimensional materials have provided new opportunities for constructing small feature-size transistors due to their superior electrical properties compared to silicon.
View Article and Find Full Text PDFSci Bull (Beijing)
May 2024
MIIT Key Laboratory of Advanced Display Materials and Devices, College of Material Science and Engineering, Nanjing University of Science and Technology, Nanjing 210094, China. Electronic address:
Developing low-power FETs holds significant importance in advancing logic circuits, especially as the feature size of MOSFETs approaches sub-10 nanometers. However, this has been restricted by the thermionic limitation of SS, which is limited to 60 mV per decade at room temperature. Herein, we proposed a strategy that utilizes 2D semiconductors with an isolated-band feature as channels to realize sub-thermionic SS in MOSFETs.
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