On-chip photonic convolution by phase-change in-memory computing cells with quasi-continuous tuning.

Matrix multiplication acceleration by on-chip (PICs) is emerging as one of the attractive and promising solutions, offering outstanding benefits in speed and bandwidth as compared to non-photonic approaches. Incorporating nonvolatile phase-change materials into PICs or devices enables optical storage and computing, surpassing their electrical counterparts. In this paper, we propose a design of on-chip photonic convolution for optical in-memory computing by integrating the phase change chalcogenide of (GSST) into an asymmetric directional coupler for constructions of an in-memory computing cell, marrying the advantages of both the large bandwidth of (MZIs) and the small size of (MRRs). Through quasi-continuous electro-thermal tuning of the GSST-integrated in-memory computing cells, numerical calculations about the optical and electro-thermal behaviors during GSST phase transition confirm the tunability of the programmable elements stored in the in-memory computing cells within [-1, 1]. For proof-of-concept verification, we apply the proposed optical convolutional kernel to a typical image edge detection application. As evidenced by the evaluation results, the prototype achieves the same accuracy as the convolution kernel implemented on a common digital computer, demonstrating the feasibility of the proposed scheme for on-chip photonic convolution and optical in-memory computing.