Herein, the structure of integrated M3D inverters are successfully demonstrated where a chemical vapor deposition (CVD) synthesized monolayer WSe p-type nanosheet FET is vertically integrated on top of CVD synthesized monolayer MoS n-type film FET arrays (2.5 × 2.5 cm) by semiconductor industry techniques, such as transfer, e-beam evaporation (EBV), and plasma etching processes. A low temperature (below 250 °C) is employed to protect the WSe and MoS channel materials from thermal decomposition during the whole fabrication process. The MoS NMOS and WSe PMOS device fabricated show an on/off current ratio exceeding 10 and the integrated M3D inverters indicate an average voltage gain of ≈9 at V = 2 V. In addition, the integrated M3D inverter demonstrates an ultra-low power consumption of 0.112 nW at a V of 1 V. Statistical analysis of the fabricated inverters devices shows their high reliability, rendering them suitable for large-area applications. The successful demonstration of M3D inverters based on large-scale 2D monolayer TMDs indicate their high potential for advancing the application of 2D TMDs in future integrated circuits.

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http://dx.doi.org/10.1002/smll.202307728DOI Listing

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