This work demonstrates the novel concept of a mixed-dimensional reconfigurable field effect transistor (RFET) by combining a one-dimensional (1D) channel material such as a silicon (Si) nanowire with a two-dimensional (2D) material as a gate dielectric. An RFET is an innovative device that can be dynamically programmed to perform as either an n- or p-FET by applying appropriate gate potentials. In this work, an insulating 2D material, hexagonal boron nitride (hBN), is introduced as a gate dielectric and encapsulation layer around the nanowire in place of a thermally grown or atomic-layer-deposited oxide. hBN flake was mechanically exfoliated and transferred onto a silicon nanowire-based RFET device using the dry viscoelastic stamping transfer technique. The thickness of the hBN flakes was investigated by atomic force microscopy and transmission electron microscopy. The ambipolar transfer characteristics of the Si-hBN RFETs with different gating architectures showed a significant improvement in the device's electrical parameters due to the encapsulation and passivation of the nanowire with the hBN flake. Both n- and p-type characteristics measured through the top gate exhibited a reduction of hysteresis by 10-20 V and an increase in the on-off ratio (/) by 1 order of magnitude (up to 10) compared to the values measured for unpassivated nanowire. Specifically, the hBN encapsulation provided improved electrostatic top gate coupling, which is reflected in the enhanced subthreshold swing values of the devices. For a single nanowire, an improvement up to 0.97 and 0.5 V/dec in the n- and p-conduction, respectively, is observed. Due to their dynamic switching and polarity control, RFETs boast great potential in reducing the device count, lowering power consumption, and playing a crucial role in advanced electronic circuitry. The concept of mixed-dimensional RFET could further strengthen its functionality, opening up new pathways for future electronics.
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http://dx.doi.org/10.1021/acsami.3c04808 | DOI Listing |
Light Sci Appl
January 2025
State Key Laboratory of Integrated Optoelectronics, College of Electronic Science and Engineering, International Center of Future Science, Jilin University, Changchun, 130012, China.
Metal-halide perovskite nanowire array photodetectors based on the solution method are valuable in the field of polarized light detection because of their unique one-dimensional array structure and excellent photoelectric performance. However, the limited wettability of liquids poses challenges for achieving large-scale and high-quality perovskite nanowire arrays. To address this issue, we develop a facile method utilizing capillary condensation to grow high-quality centimeter-scale perovskite nanowire arrays.
View Article and Find Full Text PDFNanotechnology
January 2025
Centre for Analysis and Synthesis, NanoLund, Lund University, Box 124, Lund, 221 00, SWEDEN.
Developing a reliable procedure for the growth of III-V nanowires (NW) on silicon (Si) substrates remains a significant challenge, as current methods rely on trial-and-error approaches with varying interpretations of critical process steps such as sample preparation, Au-Si alloy formation in the growth reactor, and nanowire alignment. Addressing these challenges is essential for enabling high-performance electronic and optoelectronic devices that combine the superior properties of III-V NW semiconductors with the well-established Si-based technology. Combining conventional scalable growth methods, such as Metalorganic Chemical Vapor Deposition (MOCVD) with in situ characterization using Environmental Transmission Electron Microscopy (ETEM-MOCVD) enables a deeper understanding of the growth dynamics, if that knowledge is transferable to the scalable processes.
View Article and Find Full Text PDFNat Commun
January 2025
School of Electronics Science and Engineering/National Laboratory of Solid-State Microstructures, Nanjing University, Nanjing, China.
Ultrathin silicon nanowires (diameter <30 nm) with strong electrostatic control are ideal quasi-1D channel materials for high-performance field effect transistors, while a short channel is desirable to enhance driving current. Typically, the patterning of such delicate channels relies on high-precision lithography, which is not applicable for large area electronics. In this work, we demonstrate that ultrathin and short silicon nanowires channels can be created through a local-curvature-modulated catalytic growth, where a planar silicon nanowires is directed to jump over a crossing step.
View Article and Find Full Text PDFLangmuir
January 2025
ESYCOM, CNRS-UMR 9007, Université Gustave Eiffel, F-77454 Marne-la-Vallée, France.
This study investigates the synthesis, characterization, and functional properties of well-aligned zinc oxide (ZnO) nanowires (NWs) obtained by a two-step hydrothermal method. ZnO NWs were grown on silicon substrates precoated with a ZnO seed layer. The growth process was conducted at 90 °C for different durations (2, 3, and 4 h) to examine the time-dependent evolution of the nanowire properties.
View Article and Find Full Text PDFNat Commun
January 2025
iGaN Laboratory, School of Microelectronics, University of Science and Technology of China, Hefei, PR China.
The development of an efficient and durable photoelectrode is critical for achieving large-scale applications in photoelectrochemical water splitting. Here, we report a unique photoelectrode composed of reconfigured gallium nitride nanowire-on-silicon wafer loaded with Au nanoparticles as cocatalyst that achieved an impressive applied bias photon-to-current efficiency of 10.36% under AM 1.
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