Studies of Performance of CsTiIBr (Where x = 0 to 6)-Based Mixed Halide Perovskite Solar Cell with CdS Electron Transport Layer.

The present research work represents the numerical study of the device performance of a lead-free CsTiIBr-based mixed halide perovskite solar cell (PSC), where x = 1 to 5. The open circuit voltage (V) and short circuit current (J) in a generic TCO/electron transport layer (ETL)/absorbing layer/hole transfer layer (HTL) structure are the key parameters for analyzing the device performance. The entire simulation was conducted by a SCAPS-1D (solar cell capacitance simulator- one dimensional) simulator. An alternative FTO/CdS/CsTiIBr/CuSCN/Ag solar cell architecture has been used and resulted in an optimized absorbing layer thickness at 0.5 µm thickness for the CsTiBr, CsTiIBr, CsTiIBr, CsTiIBr and CsTiIBr absorbing materials and at 1.0 µm and 0.4 µm thickness for the CsTiIBr and CsTiI absorbing materials. The device temperature was optimized at 40 °C for the CsTiBr, CsTiIBr and CsTiIBr absorbing layers and at 20 °C for the CsTiIBr, CsTiIBr, CsTiIBr and CsTiI absorbing layers. The defect density was optimized at 10 (cm) for all the active layers.