In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors.
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http://dx.doi.org/10.3390/nano12244488 | DOI Listing |
Nat Commun
January 2025
Institute of Theoretical Computer Science, Graz University of Technology, Graz, Austria.
Recent experimental studies in the awake brain have identified a rule for synaptic plasticity that is instrumental for the instantaneous creation of memory traces in area CA1 of the mammalian brain: Behavioral Time scale Synaptic Plasticity. This one-shot learning rule differs in five essential aspects from previously considered plasticity mechanisms. We introduce a transparent model for the core function of this learning rule and establish a theory that enables a principled understanding of the system of memory traces that it creates.
View Article and Find Full Text PDFACS Nano
October 2024
Department of Electrical and Information Technology, Lund University, Lund 221 00, Sweden.
Micromachines (Basel)
August 2024
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200031, China.
The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article.
View Article and Find Full Text PDFMicromachines (Basel)
July 2024
Electrical and Computer Engineering Department, Beirut Arab University, Debieh 1504, Lebanon.
Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption.
View Article and Find Full Text PDFIEEE Trans Biomed Circuits Syst
August 2024
GCOC is a genome classification system-on-chip (SoC) that classifies genomes by k-mer matching, an approach that divides a DNA query sequence into a set of short DNA fragments of size k, which are searched in a reference genome database, with the underlying assumption that sequenced DNA reads of the same organism (or its close variants) share most of such k-mers. At the core of GCOC is a similarity, or approximate search-capable Content Addressable Memory (SAS-CAM), which in addition to exact match, also supports approximate, or Hamming distance tolerant search. Classification operation is controlled by an embedded RISC-V processor.
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