Integrating a Nanowire Laser in an on-Chip Photonic Waveguide.

Nano Lett

Key Laboratory of Light Field Manipulation and Information Acquisition, Ministry of Industry and Information Technology, and Shaanxi Key Laboratory of Optical Information Technology, School of Physical Science and Technology, Northwestern Polytechnical University, Xi'an 710129, People's Republic of China.

Published: December 2022

AI Article Synopsis

  • A new method is introduced for integrating laser sources into passive photonic integrated circuits (PICs) by embedding semiconductor nanowires (NWs) in waveguides.
  • The process involves placing indium phosphide (InP) NWs on a silicon nitride (SiN) slab, covering them with a polymer, and using electron-beam lithography to create hybrid waveguides that include these NWs.
  • The resulting NW lasers demonstrate effective lasing behavior that can couple into the waveguide for applications like on-chip signal processing, providing compatibility with other PIC technologies such as silicon and lithium niobate.

Article Abstract

We report a simple and facile integration strategy of a laser source in passive photonic integrated circuits (PICs) by deterministically embedding semiconductor nanowires (NWs) in waveguides. InP NWs laid on a SiN slab are buried by a polymer layer which also acts as an electron-beam resist. With electron-beam lithography, hybrid polymer-SiN waveguides are formed with precisely embedded NWs. The lasing behavior of the waveguide-embedded NWs is confirmed, and more importantly, the NW lasing mode couples into the hybrid waveguide and forms an in-plane guiding mode. Multiple waveguide-embedded NW lasers are further integrated in complex photonic structures to illustrate that the waveguiding mode supplied by the NW lasers could be manipulated for on-chip signal processing, including power splitting and wavelength-division multiplexing. This integration strategy of an on-chip laser is applicable to other PIC platforms, such as silicon and lithium niobate, and the top cladding layer could be changed by depositing SiN or SiO, promising its CMOS compatibility.

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Source
http://dx.doi.org/10.1021/acs.nanolett.2c03364DOI Listing

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