The recent report of a p-type graphene(Gr)/carbon-nanotube(CNT) barristor facilitates the application of graphene barristors in the fabrication of complementary logic devices. Here, a complementary inverter is presented that combines a p-type Gr/CNT barristor with a n-type Gr/MoS2 barristor, and its characteristics are reported. A sub-nW (~0.2 nW) low-power inverter is demonstrated with a moderate gain of 2.5 at an equivalent oxide thickness (EOT) of ~15 nm. Compared to inverters based on field-effect transistors, the sub-nW power consumption was achieved at a much larger EOT, which was attributed to the excellent switching characteristics of Gr barristors.
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http://dx.doi.org/10.3390/nano12213820 | DOI Listing |
Adv Mater
December 2024
State Key Laboratory of Polymer Physics and Chemistry & Key Laboratory of Polymer Science and Technology, Changchun Institute of Applied Chemistry, Chinese Academy of Sciences, Changchun, 130022, P. R. China.
The charge transport of channel materials in n-type organic electrochemical transistors (OECTs) is greatly limited by the adverse effects of electrochemical doping, posing a long-standing puzzle for the community. Herein, an n-type conjugated polymer with glycolated side chains (n-PT3) is introduced. This polymer can adapt to electrochemical doping and create more organized nanostructures, mitigating the adverse effects of electrochemical doping.
View Article and Find Full Text PDFNano Lett
December 2024
Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576.
Targeting high-performance computing at cryogenic temperatures, we report back-end-of-line (BEOL)-compatible p-type Te-TeO field effect transistors (FETs) deposited using a sputtering method that is cost-effective, large-scale manufacturable, and highly controllable. Combined with the indium tin oxide channel n-FETs employing a common gate and HfO gate dielectric, BEOL three-dimensional stackable oxide semiconductor complementary metal oxide semiconductor (CMOS) inverters were further realized, demonstrating excellent threshold voltage matching, with a high voltage gain of 132 with a 2 V supply voltage () at room temperature. At cryogenic temperatures, the CMOS inverter exhibits significantly enhanced performance, achieving a voltage gain of 233 at a of 2 V with a wide noise margin of 86%.
View Article and Find Full Text PDFJ Phys Chem Lett
December 2024
College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, China.
This paper reports the utilization of cost-effective bottom-contact electrodes composed of aluminum (Al) and titanium (Ti) to facilitate efficient electron injection in n-channel organic transistors. The optimized Al/Ti electrode has a low work function of around 4.03 eV, combining the high conductivity of Al with the stable interface of Ti, making it highly suitable for the electrodes of n-channel transistors.
View Article and Find Full Text PDFSmall Methods
December 2024
Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore, 560012, India.
The intrinsic n-type behavior and unavailability of the appropriate p-type doping method for MoS allows only n-type conduction with depletion mode (D-mode) characteristics and forbids the implementation of p-type field-effect transistors (FETs). The D-mode characteristic results in a high off-current (I) at zero gate bias, which limits the usage of MoS FETs for industry-scale (n-channel metal-oxide semiconductor) NMOS/(complementary metal-oxide semiconductor) CMOS-logic-based applications due to significant power dissipation. Both these issues, i.
View Article and Find Full Text PDFSensors (Basel)
November 2024
School of Electrical Engineering, Chungbuk National University, Cheongju 28644, Republic of Korea.
This paper introduces a novel TRNG architecture that employs a wave converter to generate random outputs from the jitter noise in a customized ring oscillator (RO). Using a current-starved inverter, the proposed RO offers the option of operating three different oscillation frequencies from a single oscillator. To assess its performance, the core TRNG proposed in this work was designed with multiple samples, employing various transistor sizes for 28 nm CMOS processes.
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