Similar Publications

Building Bilayer MoS with Versatile Morphologies via Etching-And-Growth Coexisting Method.

Small

January 2025

Key Laboratory of Multiscale Spin Physics, Ministry of Education, School of Physics and Astronomy, Beijing Normal University, Beijing, 100875, P. R. China.

The etch-engineering is a feasible avenue to tailor the layer number and morphology of 2D layered materials during the chemical vapor deposition (CVD) growth. However, less reports strengthen the etch-engineering used in the fabrication of high-quality transition metal dichalcogenide (TMD) materials with tunable layers and desirable morphologies to improve their prominent performance in electronic and optoelectronic devices. Here, an etching-and-growth coexistence method is reported to directly synthesize high-quality, high-symmetric MoS bilayers with versatile morphologies via CVD.

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Wafer-scale monolayer MoS film integration for stable, efficient perovskite solar cells.

Science

January 2025

Beijing Key Laboratory for Theory and Technology of Advanced Battery Materials, Key Laboratory of Polymer Chemistry and Physics of Ministry of Education, School of Materials Science and Engineering, Peking University, Beijing, China.

One of the primary challenges in commercializing perovskite solar cells (PSCs) is achieving both high power conversion efficiency (PCE) and sufficient stability. We integrate wafer-scale continuous monolayer MoS buffers at the top and bottom of a perovskite layer through a transfer process. These films physically block ion migration of perovskite into carrier transport layers and chemically stabilize the formamidinium lead iodide phase through strong coordination interaction.

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MoS, one of the most researched two-dimensional semiconductor materials, has great potential as the channel material in dynamic random-access memory (DRAM) due to the low leakage current inherited from the atomically thin thickness, high band gap, and heavy effective mass. In this work, we fabricate one-transistor-one-capacitor (1T1C) DRAM using chemical vapor deposition (CVD)-grown monolayer (ML) MoS in large area and confirm the ultralow leakage current of approximately 10 A/μm, significantly lower than the previous report (10 A/μm) in two-transistor-zero-capacitor (2T0C) DRAM based on a few-layer MoS flake. Through rigorous analysis of leakage current considering thermionic emission, tunneling at the source/drain, Shockley-Read-Hall recombination, and trap-assisted tunneling (TAT) current, the TAT current is identified as the primary source of leakage current.

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Increasing attention to sustainability and cost-effectiveness in energy storage sector has catalyzed the rise of rechargeable Zinc-ion batteries (ZIBs). However, finding replacement for limited cycle-life Zn-anode is a major challenge. Molybdenum disulfide (MoS), an insertion-type 2D layered material, has shown promising characteristics as a ZIB anode.

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Different temperatures leakage mechanisms of (AlO)(HfO) gate Dielectrics deposited by atomic layer deposition.

Sci Rep

January 2025

Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, Xidian University, Xi'an, 710071, China.

(AlO)(HfO) films with varying compositions were deposited on silicon substrates via plasma-enhanced atomic layer deposition (PEALD), and metal-oxide-semiconductor (MOS) capacitors were fabricated. The impact of varying induced Al content on the dielectric properties of HfO was examined through electrical measurements. The results showed that increasing Al content raised the flat-band voltage, reduced the interface state density (D), and significantly lowered the leakage current at a given voltage.

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