The explosion in demand for massive data processing and storage requires revolutionary memory technologies featuring ultrahigh speed, ultralong retention, ultrahigh capacity and ultralow energy consumption. Although a breakthrough in ultrafast floating-gate memory has been achieved very recently, it still suffers a high operation voltage (tens of volts) due to the Fowler-Nordheim tunnelling mechanism. It is still a great challenge to realize ultrafast nonvolatile storage with low operation voltage. Here we propose a floating-gate memory with a structure of MoS/hBN/MoS/graphdiyne oxide/WSe, in which a threshold switching layer, graphdiyne oxide, instead of a dielectric blocking layer in conventional floating-gate memories, is used to connect the floating gate and control gate. The volatile threshold switching characteristic of graphdiyne oxide allows the direct charge injection from control gate to floating gate by applying a nanosecond voltage pulse (20 ns) with low magnitude (2 V), and restricts the injected charges in floating gate for a long-term retention (10 years) after the pulse. The high operation speed and low voltage endow the device with an ultralow energy consumption of 10 fJ. These results demonstrate a new strategy to develop next-generation high-speed low-energy nonvolatile memory.
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http://dx.doi.org/10.1038/s41467-022-32380-3 | DOI Listing |
Micromachines (Basel)
December 2024
Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, 20133 Milan, Italy.
Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase.
View Article and Find Full Text PDFACS Appl Mater Interfaces
January 2025
Key Laboratory of Materials Chemistry for Energy Conversion and Storage of Ministry of Education (HUST), State Key Laboratory of Materials Processing and Die & Mold Technology, and Hubei Key Laboratory of Materials Chemistry and Service Failure, School of Chemistry and Chemical Engineering, Huazhong University of Science and Technology (HUST), Wuhan 430074, China.
Polymer/gold nanoparticle (AuNP) composites have been utilized as floating gates to enhance the performance of memory devices. However, these devices typically exhibit a low ON/OFF drain current ratio (/) and unstable charge trapping, attributed to the poorly defined arrangement of AuNPs within the composite floating gate. To address these limitations, this study employs poly(methyl methacrylate)-grafted AuNPs (Au@PMMA) as building blocks for the fabrication of monolayered superlattice films with a highly ordered structure via liquid/liquid interfacial assembly.
View Article and Find Full Text PDFHeliyon
February 2024
Department of Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), Ho Chi Minh City, 72506, Viet Nam.
An automatic programming tool has become an essential component in virtual fabrication in recent years. This paper aims to propose a methodology of virtual fabrication for semiconductor devices and design a tool called Technology Computer-Aided Design Automatic Simulation (TCADAS) which can perform a completely virtual fabrication, device simulation, process variation, and output extraction. Especially, the TCADAS tool eliminates drudgery when studying semiconductor devices such as complexity in setting inputs, substantial manual work, and long run time of simulations.
View Article and Find Full Text PDFNanomicro Lett
November 2024
Department of Organic and Nano Engineering & Human-Tech Convergence Program, Hanyang University, Seoul, 04763, Korea.
To emulate the functionality of the human retina and achieve a neuromorphic visual system, the development of a photonic synapse capable of multispectral color discrimination is of paramount importance. However, attaining robust color discrimination across a wide intensity range, even irrespective of medium limitations in the channel layer, poses a significant challenge. Here, we propose an approach that can bestow the color-discriminating synaptic functionality upon a three-terminal transistor flash memory even with enhanced discriminating capabilities.
View Article and Find Full Text PDFACS Nano
December 2024
Hunan Institute of Advanced Sensing and Information Technology, Hunan Provincial Key Laboratory of Smart Carbon Materials and Advanced Sensing, Xiangtan University, Hunan 411105, China.
Field-effect transistor (FET) sensors are attractive for the label-free detection of target biomolecules, offering ultrahigh sensitivity and a rapid response. However, conventional methods for modifying biomolecular probes on sensors often involve intricate and time-consuming procedures that require specialized training. Herein, we propose a simple and versatile approach to functionalize floating-gate (FG) FET sensors by exploiting the strong binding ability of polyvalent interactions and the three-dimensional structure of densely functionalized spherical nucleic acids (SNAs).
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