Clean BN-Encapsulated 2D FETs with Lithography-Compatible Contacts.

ACS Appl Mater Interfaces

National Laboratory of Solid-State Microstructures and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, Jiangsu 210023, China.

Published: April 2022

Device passivation through ultraclean hexagonal BN encapsulation has proven to be one of the most effective ways of constructing high-quality devices with atomically thin semiconductors that preserve the ultraclean interface quality and intrinsic charge transport behavior. However, it remains challenging to integrate lithography-compatible contact electrodes with flexible distributions and patterns. Here, we report the feasibility of a straightforward integration of lithography-defined contacts into BN-encapsulated two-dimensional field-effect transistors (2D FETs), giving rise to overall device quality comparable to the state-of-the-art results from the painstaking pure dry transfer processing. The electronic characterization of FETs consisting of WSe and MoS channels reveals an extremely low scanning hysteresis of ∼2 mV on average, a low density of interfacial charged impurities of ∼10 cm, and generally high charge mobilities over 1000 cm V s at low temperatures. The overall high device qualities verify the viability of directly integrating lithography-defined contacts into BN-encapsulated devices to exploit their intrinsic charge transport properties for advanced electronics.

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http://dx.doi.org/10.1021/acsami.2c02956DOI Listing

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