Defect Engineering in Thickness-Controlled BiOSe-Based Transistors by Argon Plasma Treatment.

We present a simple, effective, and controllable method to uniformly thin down the thickness of as-exfoliated two-dimensional BiOSe nanoflakes using Ar plasma treatment. Atomic force microscopy (AFM) images and Raman spectra indicate that the surface morphology and crystalline quality of etched BiOSe nanoflakes remain almost unaffected. X-ray photoelectron spectra (XPS) indicate that the O and Se vacancies created during Ar plasma etching on the top surface of BiOSe nanoflakes are passivated by forming an ultrathin oxide layer with UV O treatment. Moreover, a bottom-gate BiOSe-based field-effect transistor (FET) was constructed to research the effect of thicknesses and defects on electronic properties. The on-current/off-current (/) ratio of the BiOSe FET increases with decreasing BiOSe thickness and is further improved by UV O treatment. Eventually, the thickness-controlled BiOSe FET achieves a high / ratio of 6.0 × 10 and a high field-effect mobility of 5.7 cm V s. Specifically, the variation trend of the / ratio and the electronic transport properties for the bottom-gate BiOSe-based FET are well described by a parallel resistor model (including bulk, channel, and defect resistance). Furthermore, the - hysteresis and its inversion with UV irradiation were observed. The pulsed gate and drain voltage measurements were used to extract trap time constants and analyze the formation mechanism of different hysteresis. Before UV irradiation, the origin of clockwise hysteresis is attributed to the charge trapping/detrapping of defects at the BiOSe/SiO interface and in the BiOSe bulk. After UV irradiation, the large anticlockwise hysteresis is mainly due to the tunneling between deep-level oxygen defects in SiO and p-Si gate, which implies the potential in nonvolatile memory.