Induced Complementary Resistive Switching in Forming-Free TiO/TiO/TiO Memristors.

ACS Appl Mater Interfaces

WATLab and Department of Chemistry, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1, Canada.

Published: September 2021

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Article Abstract

The undesirable sneak current path is one of the key challenges in high-density memory integration for the emerging cross-bar memristor arrays. This work demonstrates a new heterojunction design of oxide multilayer stacking with different oxygen vacancy contents to manipulate the oxidation state. We show that the bipolar resistive switching (BRS) behavior of the Pt/TiO/Pt cross-bar structure can be changed to complementary resistive switching (CRS) by introducing a thin TiO layer in the middle of the TiO layer to obtain a Pt/TiO/TiO/TiO/Pt device architecture with a double-junction active matrix. In contrast to the BRS in a single-layer TiO matrix, the device with a double-junction matrix remains in a high-resistance state in the voltage range below the SET voltage, which makes it an efficient structure to overcome the sneak path constraints of undesired half-selected cells that lead to incorrect output reading. This architecture is capable of eliminating these half-selected cells between the nearby cross-bar cells in a smaller programming voltage range. A simplified model for the switching mechanism can be used to account for the observed high-quality switching performance with excellent endurance and current retention properties.

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http://dx.doi.org/10.1021/acsami.1c09775DOI Listing

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