Polarity Control and Weak Fermi-Level Pinning in PdSe Transistors.

ACS Appl Mater Interfaces

Department of System Semiconductor Engineering, Yonsei University, Seoul 03722, South Korea.

Published: September 2021

Two-dimensional (2D) materials have been considered key materials for the future logic devices due to the excellent electrostatic integrity originating from their ultrathin nature. However, the carrier polarity control of 2D material field-effect transistors (FETs) still remains a challenging issue, hindering the realization of complementary logic function in the 2D material platform. Here, we report a comprehensive study on the electrical characteristics of PdSe FETs with different metal contacts. It is found that the carrier polarity in PdSe FETs can be modulated simply by changing the metal contact due to the weak Fermi-level pinning in PdSe. We demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter using the same channel material PdSe for n- and p-MOSFETs but with different metal contacts, suggesting the possible realization of PdSe-based CMOS logic circuits.

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Source
http://dx.doi.org/10.1021/acsami.1c08028DOI Listing

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