Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS.

ACS Appl Mater Interfaces

Department of Electrical Engineering, Stanford University, Stanford, California 94305, United States.

Published: September 2021

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS films at 560 °C in 50 min, within the 450-to-600 °C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ∼140 μA/μm at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS grown below 600 °C using solid-source precursors. The effective mobility from transfer length method test structures is 29 ± 5 cm V s at 6.1 × 10 cm electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

Download full-text PDF

Source
http://dx.doi.org/10.1021/acsami.1c06812DOI Listing

Publication Analysis

Top Keywords

monolayer mos
8
heterogeneous integration
8
silicon technology
8
low-temperature solid-source
4
solid-source synthesis
4
synthesis monolayer
4
mos two-dimensional
4
two-dimensional semiconductors
4
semiconductors proposed
4
proposed heterogeneous
4

Similar Publications

Want AI Summaries of new PubMed Abstracts delivered to your In-box?

Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!