Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.
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http://dx.doi.org/10.3390/mi12040414 | DOI Listing |
Sensors (Basel)
January 2025
Institute of Automatic Control, Lodz University of Technology, 90-537 Lodz, Poland.
Warping is a crucial process that connects two main stages of production: yarn manufacturing and fabric creation. Two interrelated parameters affect the efficiency of this technological process: warping speed and the ability to swiftly detect the yarn breaks caused by various defects. The faster a break is detected and the warping machine stopped, the higher the machine's working speed can be.
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January 2025
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China.
High-precision, low-power MEMS accelerometers are extensively utilized across civilian applications. Closed-loop accelerometers employing switched-capacitor (SC) circuit topologies offer notable advantages, including low power consumption, high signal-to-noise ratio (SNR), and excellent linearity. Addressing the critical demand for high-precision, low-power MEMS accelerometers in modern geophones, this work focuses on the design and implementation of closed-loop interface ASICs (Application-Specific Integrated Circuits).
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January 2025
Department of Information Engineering, University of Brescia, 25121 Brescia, Italy.
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December 2024
International Iberian Nanotechnology Laboratory, 4715-330 Braga, Portugal.
The development of low-temperature piezoresistive materials provides compatibility with standard silicon-based MEMS fabrication processes. Additionally, it enables the use of such material in flexible substrates, thereby expanding the potential for various device applications. This work demonstrates, for the first time, the fabrication of a 200 nm polycrystalline silicon thin film through a metal-induced crystallization process mediated by an AlSiCu alloy at temperatures as low as 450 °C on top of silicon and polyimide (PI) substrates.
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December 2024
Institute of Nanostructure Technologies and Analytics (INA), Technological Electronics Department and Center for Interdisciplinary Nanostructure Science and Technology (CINSaT), University of Kassel, Heinrich-Plett-Straße 40, 34132 Kassel, Germany.
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