Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal-oxide-semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.
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http://dx.doi.org/10.3390/mi11100925 | DOI Listing |
Front Bioeng Biotechnol
November 2024
Electrical and Computer Engineering Department, Integrated Circuits and Bioengineering Laboratory, Carnegie Mellon University, Pittsburgh, PA, United States.
Biosensors translate biological events into electronic signals that quantify biological processes. They are increasingly used in diagnostics applications that leverage their ability to process small sample volumes. One recent trend has been to integrate biosensors with complementary metal-oxide-semiconductor (CMOS) chips to provide enhanced miniaturization, parallel sensing, and low power consumption at a low cost.
View Article and Find Full Text PDFACS Nano
September 2024
Department of Chemical and Biological Engineering, Seoul National University, Seoul 08826, Republic of Korea.
The persistent challenges encountered in metal-transition-metal dichalcogenide (TMD) junctions, including tunneling barriers and Fermi-level pinning, pose significant impediments to achieving optimal charge transport and reducing contact resistance. To address these challenges, a pioneering self-aligned edge contact (SAEC) process tailored for TMD-based field-effect transistors (FETs) is developed by integrating a WS semiconductor with a hexagonal boron nitride dielectric via reactive ion etching. This approach streamlines semiconductor fabrication by enabling edge contact formation without the need for additional lithography steps.
View Article and Find Full Text PDFIEEE Trans Biomed Circuits Syst
April 2024
This article presents the system architecture for an implant concept called NeuroBus. Tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible polyimide substrate are connected in a bus-like structure, allowing short connections between electrode and recording front-end with low wiring effort and high customizability. The small size (344 μm × 294 μm) of the ASICs and the ultraflexible substrate allow a low bending stiffness, enabling the implant to adapt to the curvature of the brain and achieving high structural biocompatibility.
View Article and Find Full Text PDFMicrosyst Nanoeng
November 2023
Department of Microsystems, University of South-Eastern Norway, 3184 Horten, Norway.
Carbon nanotubes (CNTs) can be locally grown on custom-designed CMOS microheaters by a thermal chemical vapour deposition (CVD) process to utilize the sensing capabilities of CNTs in emerging micro- and nanotechnology applications. For such a direct CMOS-CNT integration, a key requirement is the development of necessary post-processing steps on CMOS chips for fabricating CMOS-MEMS polysilicon heaters that can locally generate the required CNT synthesis temperatures (~650-900 °C). In our post-CMOS processing, a subtractive fabrication technique is used for micromachining the polysilicon heaters, where the passivation layers in CMOS are used as masks to protect the electronics.
View Article and Find Full Text PDFAdv Sci (Weinh)
December 2023
School of Engineering, Brown University, Providence, RI, 02912, USA.
Wearable and implantable microscale electronic sensors have been developed for a range of biomedical applications. The sensors, typically millimeter size silicon microchips, are sought for multiple sensing functions but are severely constrained by size and power. To address these challenges, a hardware programmable application-specific integrated circuit design is proposed and post-process methodology is exemplified by the design of battery-less wireless microchips.
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