Quantum circuit optimization using quantum Karnaugh map.

Sci Rep

Department of Physics, Florida Atlantic University, Boca Raton, FL, 33431, USA.

Published: September 2020

Every quantum algorithm is represented by set of quantum circuits. Any optimization scheme for a quantum algorithm and quantum computation is very important especially in the arena of quantum computation with limited number of qubit resources. Major obstacle to this goal is the large number of elemental quantum gates to build even small quantum circuits. Here, we propose and demonstrate a general technique that significantly reduces the number of elemental gates to build quantum circuits. This is impactful for the design of quantum circuits, and we show below this could reduce the number of gates by 60% and 46% for the four- and five-qubit Toffoli gates, two key quantum circuits, respectively, as compared with simplest known decomposition. Reduced circuit complexity often goes hand-in-hand with higher efficiency and bandwidth. The quantum circuit optimization technique proposed in this work would provide a significant step forward in the optimization of quantum circuits and quantum algorithms, and has the potential for wider application in quantum computation.

Download full-text PDF

Source
http://www.ncbi.nlm.nih.gov/pmc/articles/PMC7518448PMC
http://dx.doi.org/10.1038/s41598-020-72469-7DOI Listing

Publication Analysis

Top Keywords

quantum circuits
24
quantum
16
quantum computation
12
quantum circuit
8
circuit optimization
8
optimization quantum
8
quantum algorithm
8
number elemental
8
gates build
8
circuits
6

Similar Publications

Optimization of In-Situ Growth of Superconducting Al/InAs Hybrid Systems on GaAs for the Development of Quantum Electronic Circuits.

Materials (Basel)

January 2025

CNR-IOM-Istituto Officina dei Materiali, Consiglio Nazionale delle Ricerche, 34149 Trieste, Italy.

Hybrid systems consisting of highly transparent channels of low-dimensional semiconductors between superconducting elements allow the formation of quantum electronic circuits. Therefore, they are among the novel material platforms that could pave the way for scalable quantum computation. To this aim, InAs two-dimensional electron gases are among the ideal semiconductor systems due to their vanishing Schottky barrier; however, their exploitation is limited by the unavailability of commercial lattice-matched substrates.

View Article and Find Full Text PDF

Hybrid superconductor-semiconductor Josephson field-effect transistors (JoFETs) function as Josephson junctions with gate-tunable critical current. Additionally, they can feature a non-sinusoidal current-phase relation (CPR) containing multiple harmonics of the superconducting phase difference, a so-far underutilized property. Here we exploit this multi-harmonicity to create a Josephson circuit element with an almost perfectly π-periodic CPR, indicative of a largely dominant charge-4e supercurrent transport.

View Article and Find Full Text PDF

A notable feature of systems with non-Hermitian skin effects is the sensitivity to boundary conditions. In this work, we introduce one type of boundary condition provided by a coupling impurity. We consider a system where a two-level system as an impurity couples to a nonreciprocal Su-Schrieffer-Heeger chain under periodic boundary conditions at two points with asymmetric couplings.

View Article and Find Full Text PDF

A rear emitter with a p-type boron-doped hydrogenated amorphous silicon/nanocrystalline silicon [a-Si:H(p)/nc-Si:H(p)] stack was prepared for the silicon heterojunction (SHJ) solar cell to improve its short-circuit current density (). CO plasma treatment (CO PT) was applied to a-Si:H(p) to facilitate the crystallization of the subsequently deposited nc-Si:H(p). To evaluate the effect of the CO PT, two different nc-Si:H(p) layers with low and high crystallinity (χ) were investigated.

View Article and Find Full Text PDF

Inverse design via topology optimization has led to innovations in integrated photonics and offers a promising way for designing high-efficiency on-chip couplers with a minimal footprint. In this work, we exploit topology optimization to design a compact vertical coupler incorporating a bottom reflector, which achieves sub-decibel coupling efficiency on the 220-nm silicon-on-insulator platform. The final design of the vertical coupler yields a predicted coupling efficiency of -0.

View Article and Find Full Text PDF

Want AI Summaries of new PubMed Abstracts delivered to your In-box?

Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!