On-Chip TaO -Based Non-volatile Resistive Memory for Neurointerfaces.

The development of highly integrated electrophysiological devices working in direct contact with living neuron tissue opens new exciting prospects in the fields of neurophysiology and medicine, but imposes tight requirements on the power dissipated by electronics. preprocessing of neuronal signals can substantially decrease the power dissipated by external data interfaces, and the addition of embedded non-volatile memory would significantly improve the performance of a co-processor in real-time processing of the incoming information stream from the neuron tissue. Here, we evaluate the parameters of TaO -based resistive switching (RS) memory devices produced by magnetron sputtering technique and integrated with the 180-nm CMOS field-effect transistors as possible candidates for on-chip memory in the hybrid neurointerface under development. The electrical parameters of the optimized one-transistor-one-resistor (1T-1R) devices, such as the switching voltage (approx. ±1 V), uniformity of the / ratio (∼10), read/write speed (<40 ns), and the number of the writing cycles (up to 10), are satisfactory. The energy values for writing and reading out a bit ∼30 and ∼0.1 pJ, respectively, are also suitable for the desired neurointerfaces, but are still far too high once the prospective applications are considered. Challenges arising in the course of the prospective fabrication of the proposed TaO -based RS devices in the back-end-of-line process are identified.