High-Performance Field-Effect Transistor and Logic Gates Based on GaS-MoS van der Waals Heterostructure.

This work demonstrates a high-performance and hysteresis-free field-effect transistor based on two-dimensional (2D) semiconductors featuring a van der Waals heterostructure, MoS channel, and GaS gate insulator. The transistor exhibits a subthreshold swing of 63 mV/dec, an on/off ratio over 10 within a gate voltage of 0.4 V, and peak mobility of 83 cm/(V s) at room temperature. The low-frequency noise characteristics were investigated and described by the Hooge mobility fluctuation model. The results suggest that the van der Waals heterostructure of 2D semiconductors can produce a high-performing interface without dangling bonds and defects caused by lattice mismatch. Furthermore, a logic inverter and a NAND gate are demonstrated, with an inverter voltage gain of 14.5, which is higher than previously reported by MoS-based transistors with oxide dielectrics. Therefore, this transistor based on van der Waals heterostructure exhibits considerable potential in digital logic applications with low-power integrated circuits.