Improved electrical performance of a sol-gel IGZO transistor with high-k AlO gate dielectric achieved by post annealing.

We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an AlO bottom gate dielectric, formed by a sol-gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance-voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (V) and the hydroxyl groups (M-OH) within the IGZO/AlO layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns V, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol-gel oxide transistor.