Optimal device integrity was achieved in Ni/SiGeO/TiO/TaN resistive memory by using a forming-free switch with a low switching power of 790 W, stable endurance of 104 cycles, optimal retention time of 105 s, resistance window of at least 1150×, and tight current distributions at 85 °C. These characteristics are attributed to the low current switching obtained using SiGeO with a high oxygen vacancy density and highly defective TiO grain boundaries.
Download full-text PDF |
Source |
|---|---|
| http://dx.doi.org/10.1166/jnn.2019.16781 | DOI Listing |
Publication Analysis
Top Keywords
Similar Publications
Forming-Free SiGeO/TiO Resistive Random Access Memories Featuring Large Current Distribution Windows.
J Nanosci Nanotechnol
December 2019
Department of Materials & Mineral Resources Engineering, National Taipei University of Technology, Taipei 10608, Taiwan.
Optimal device integrity was achieved in Ni/SiGeO/TiO/TaN resistive memory by using a forming-free switch with a low switching power of 790 W, stable endurance of 104 cycles, optimal retention time of 105 s, resistance window of at least 1150×, and tight current distributions at 85 °C. These characteristics are attributed to the low current switching obtained using SiGeO with a high oxygen vacancy density and highly defective TiO grain boundaries.
View Article and Find Full Text PDFWant AI Summaries of new PubMed Abstracts delivered to your In-box?
Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!