The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiO as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide.

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium-tin-zinc-oxide (ITZO) as an active channel layer and multi-oxide structure of SiO (blocking layer)/Si-rich SiO (charge trapping layer)/SiON (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH:NO, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal-insulator-silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH:NO = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (Δ) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiO charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 10 were obtained at the initial sweep of the devices. As an NVM, Δ was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The Δ was returned to the pristine condition with a negative voltage pulse of -1 V and 1 μs under a 400-700 nm light illumination of ~10 mWcm in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial Δ (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.