Vertical Tunnel Field-Effect Transistor with Polysilicon Layer.

In this paper, a novel structure of tunnel field-effect transistors (TFETs) is proposed. The proposed device has an intrinsic polysilicon layer located in the overlap region between the source and the gate, which can increase the tunneling area and overcome the low ON-current drawback of the conventional TFET. The advantages of the proposed device are proven by using technology computeraided design (TCAD) simulation. It exhibits more than 50 higher on-current () of 0.13 A/m and lower subthreshold swing (SS) of 53 mV/dec than a conventional planar TFET. In addition, the effect of some device parameters on the device performance has been investigated.