Despite being a fundamental electronic component for over 70 years, it is still possible to develop different transistor designs, including the addition of a diode-like Schottky source electrode to thin-film transistors. The discovery of a dependence of the source barrier height on the semiconductor thickness and derivation of an analytical theory allow us to propose a design rule to achieve extremely high voltage gain, one of the most important figures of merit for a transistor. Using an oxide semiconductor, an intrinsic gain of 29,000 was obtained, which is orders of magnitude higher than a conventional Si transistor. These same devices demonstrate almost total immunity to negative bias illumination temperature stress, the foremost bottleneck to using oxide semiconductors in major applications, such as display drivers. Furthermore, devices fabricated with channel lengths down to 360 nm display no obvious short-channel effects, another critical factor for high-density integrated circuits and display applications. Finally, although the channel material of conventional transistors must be a semiconductor, by demonstrating a high-performance transistor with a semimetal-like indium tin oxide channel, the range and versatility of materials have been significantly broadened.
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http://dx.doi.org/10.1073/pnas.1820756116 | DOI Listing |
Sensors (Basel)
December 2024
Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea.
In this paper, a sub-1dB Low Noise Amplifier (LNA) with several gain modes, including amplification and attenuation modes required for the fifth and fourth generations (5G/4G) of mobile network applications, is proposed. Its current consumption is adaptive for every gain mode and varies to lower currents for lower amplifications due to the importance of current consumption for mobile network applications. The proposed LNA features an innovative architecture with a three-core input structure supporting multi-gain modes, achieving high gain and ultra-low noise performance.
View Article and Find Full Text PDFMaterials (Basel)
November 2024
State Key Laboratory of Extreme Photonics and Instrumentation, ZJU-Hangzhou Global Scientific and Technological Innovation Center, Zhejiang University, Hangzhou 310027, China.
Nat Mater
November 2024
Key Laboratory of Artificial Micro- and Nano-structures of Ministry of Education and School of Physics and Technology, Wuhan University, Wuhan, China.
The downscaling of complementary metal-oxide-semiconductor technology has produced breakthroughs in electronics, but more extreme scaling has hit a wall of device performance degradation. One key challenge is the development of insulators with high dielectric constant, wide bandgap and high tunnel masses. Here, we show that two-dimensional monocrystalline gadolinium pentoxide, which is devised through combining particle swarm optimization algorithm and theoretical calculations and synthesized via van der Waals epitaxy, could exhibit a high dielectric constant of ~25.
View Article and Find Full Text PDFISA Trans
January 2025
Electrical & Electronics Engineering, Ege University, Izmir, Turkey. Electronic address:
Control of the family of systems that can be represented in the Euler Lagrange (EL) form is both challenging from a theoretical perspective and applicable to a broad spectrum of real systems. For this type of control problem, given that any parameter estimation error and disturbances are not directly addressed, the system performance deteriorates, and stability cannot be deduced in advance. Considering these issues, this work presents the design and the corresponding analysis of a saturation function based, model-free, continuous robust controller for mechanical systems represented in the EL form.
View Article and Find Full Text PDFACS Nano
August 2024
Department of Materials Science and Engineering, Yonsei University, Seoul 03722, South Korea.
In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS field-effect transistors (FETs). Our large-area CVD-grown monolayer WS FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlO/AlO and a double-gate structure employing high- dielectric HfO.
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