In the present study, we quantitatively evaluated dielectric breakdown in silicon-based micro- and nanofluidic devices under practical electrophoretic conditions by changing the thickness of the insulating layer. At higher buffer concentration, a silicon nanofluidic device with a 100 nm or 250 nm silicon dioxide layer tolerated dielectric breakdown up to ca. 10 V/cm, thereby allowing successful electrophoretic migration of a single DNA molecule through a nanochannel. The observed DNA migration behavior suggested that parameters, such as thickness of the insulating layer, tolerance of dielectric breakdown, and bonding status of silicon and glass substrate, should be optimized to achieve successful electrophoretic transport of a DNA molecule through a nanopore for nanopore-based DNA sequencing applications.
Download full-text PDF |
Source |
|---|---|
| http://www.ncbi.nlm.nih.gov/pmc/articles/PMC6187859 | PMC |
| http://dx.doi.org/10.3390/mi9040180 | DOI Listing |
Publication Analysis
Top Keywords
Similar Publications
Enhanced Dielectric Performance in PVDF-Based Composites by Introducing a Transition Interface.
Polymers (Basel)
January 2025
School of Computer Engineering, Weifang University, Weifang 261061, China.
Polymeric dielectrics have garnered significant interest worldwide due to their excellent comprehensive performance. However, developing polymeric dielectric films with high permittivity () and breakdown strength () and low dielectric loss (tan) presents a huge challenge. In this study, amorphous aluminum oxide (AlO, AO) transition interfaces with nanoscale thickness were constructed between titanium oxide (TiO, TO) nanosheets and polyvinylidene fluoride (PVDF) to manufacture composites (PVDF/TO@AO).
View Article and Find Full Text PDFShort-Circuit Performance Analysis of Commercial 1.7 kV SiC MOSFETs Under Varying Electrical Stress.
Micromachines (Basel)
January 2025
College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China.
The short-circuit (SC) robustness of SiC MOSFETs is critical for high-power applications, yet 1.2 kV devices often struggle to meet the industry-standard SC withstand time (SCWT) under practical operating conditions. Despite growing interest in higher voltage classes, no prior study has systematically evaluated the SC performance of 1.
View Article and Find Full Text PDFReal-Time Monitoring Method and Circuit Based on Built-In Reliability Prediction.
Micromachines (Basel)
December 2024
School of Microelectronics, Xidian University, Xi'an 710071, China.
The failure of different chips under working conditions is influenced by various stress states such as different voltages, temperatures, stress durations, and stress variations. Therefore, the failure time has a great degree of dispersion, and similar chips may exhibit different failure mechanisms due to variations in their working environments. This paper proposes three system-on-chip reliability failure prediction unit circuits: the time-dependent dielectric breakdown prediction circuit, the negative bias temperature instability prediction circuit, and the hot carrier injection prediction circuit.
View Article and Find Full Text PDFBulk thermally conductive polyethylene as a thermal interface material.
Mater Horiz
January 2025
Sibley School of Mechanical and Aerospace Engineering, Cornell University, Ithaca, New York 14853, USA.
As the demand for high-power-density microelectronics rises, overheating becomes the bottleneck that limits device performance. In particular, the heterogeneous integration architecture can magnify the importance of heat dissipation and necessitate electrical insulation between critical junctions to prevent dielectric breakdown. Consequently, there is an urgent need for thermal interface materials (TIMs) with high thermal conductivity and electrical insulation to address this challenge.
View Article and Find Full Text PDFUltralow Power Cold-Fuse Memory Based on Metal-Oxide-CNT Structure.
Nano Lett
January 2025
Key Lab for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China.
One-time programmable (OTP) memory is an essential component in chips, which has extremely high security to protect the stored critical information from being altered. However, traditional OTP memory based on the thermal breakdown of the dielectric has a large programming current, which leads to high power consumption. Here, we report a gate tunneling-induced "cold" breakdown phenomenon in carbon nanotube (CNT) field-effect transistors, and based on this we construct a "cold" fuse (C-fuse) memory where applying a mild gate voltage can break down the CNT channel without damaging the gate dielectric.
View Article and Find Full Text PDFWant AI Summaries of new PubMed Abstracts delivered to your In-box?
Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!