We fabricated MoS-based flash memory devices by stacking MoS and hexagonal boron nitride (hBN) layers on an hBN/Au substrate and demonstrated that these devices can emulate various biological synaptic functions, including potentiation and depression processes, spike-rate-dependent plasticity, and spike-timing dependent plasticity. In particular, compared to a flash memory device prepared on an hBN substrate, the device fabricated on the hBN/Au exhibited considerably more symmetric and linear bidirectional gradual conductance change curves, which may be attributed to the device structure incorporating double floating gate. For the device on the hBN/Au, electron transfers may occur between the floating gate MoS and Au, as well as between the floating gate MoS and the channel MoS, allowing for more control over electron tunneling and injection. To test our hypothesis, we also fabricated a MoS-based flash memory device on an hBN/Pd substrate and found behavior similar to the device fabricated on hBN/Au. Our results demonstrate that flexible synaptic electronics may be implemented using MoS-based flash memory devices with double floating gates.
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Bioengineering (Basel)
December 2024
Department of Electrical Engineering and Information Technology (DIETI), University of Naples Federico II, 80125 Naples, Italy.
Diabetes is a chronic condition, and traditional monitoring methods are invasive, significantly reducing the quality of life of the patients. This study proposes the design of an innovative system based on a microcontroller that performs real-time ECG acquisition and evaluates the presence of diabetes using an Edge-AI solution. A spectrogram-based preprocessing method is combined with a 1-Dimensional Convolutional Neural Network (1D-CNN) to analyze the ECG signals directly on the device.
View Article and Find Full Text PDFCortex
January 2025
The School of Psychological Sciences, Tel Aviv University, Tel Aviv, Israel; The Sagol School of Neuroscience, Tel Aviv University, Tel Aviv, Israel.
To access its online representations, visual working memory (VWM) relies on a pointer-system that creates correspondence between objects in the environment with their memory representations. This pointer-system allows VWM to modify its representations using a process called updating. When the pointer is invalidated, however, VWM triggers a process called resetting in which the no longer relevant representation and pointer are replaced.
View Article and Find Full Text PDFACS Appl Mater Interfaces
January 2025
Department of Electronic Engineering, Hanyang University, Seoul 04763, Republic of Korea.
For potential application in advanced memory devices such as dynamic random-access memory (DRAM) or NAND flash, nanolaminated indium oxide (In-O) and gallium oxide (Ga-O) films with five different vertical cation distributions were grown and investigated by using a plasma-enhanced atomic layer deposition (PEALD) process. Specifically, this study provides an in-depth examination of how the control of individual layer thicknesses in the nanolaminated (NL) IGO structure impacts not only the physical and chemical properties of the thin film but also the overall device performance. To eliminate the influence of the cation composition ratio and overall thickness on the IGO thin film, these parameters were held constant across all conditions.
View Article and Find Full Text PDFPhilos Trans A Math Phys Eng Sci
January 2025
Microsystems Group, School of Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU, UK.
The increasing demand for processing large volumes of data for machine learning (ML) models has pushed data bandwidth requirements beyond the capability of traditional von Neumann architecture. In-memory computing (IMC) has recently emerged as a promising solution to address this gap by enabling distributed data storage and processing at the micro-architectural level, significantly reducing both latency and energy. In this article, we present In-Memory comPuting architecture based on Y-FlAsh technology for Coalesced Tsetlin machine inference (IMPACT), underpinned on a cutting-edge memory device, Y-Flash, fabricated on a 180 nm complementary metal oxide semiconductor (CMOS) process.
View Article and Find Full Text PDFMicromachines (Basel)
December 2024
Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, 20133 Milan, Italy.
Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase.
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