Multivalued logic (MVL) devices/circuits have received considerable attention because the binary logic used in current Si complementary metal-oxide-semiconductor (CMOS) technology cannot handle the predicted information throughputs and energy demands of the future. To realize MVL, the conventional transistor platform needs to be redesigned to have two or more distinctive threshold voltages (Vs). Here, we report a finding: the photoinduced drain current in graphene/WSe heterojunction transistors unusually decreases with increasing gate voltage under illumination, which we refer to as the light-induced negative differential transconductance (L-NDT) phenomenon. We also prove that such L-NDT phenomenon in specific bias ranges originates from a variable potential barrier at a graphene/WSe junction due to a gate-controllable graphene electrode. This finding allows us to conceive graphene/WSe-based MVL logic circuits by using the I-V characteristics with two distinctive Vs. Based on this finding, we further demonstrate a light-triggered ternary inverter circuit with three stable logical states (ΔV of each state <0.05 V). Our study offers the pathway to substantialize MVL systems.
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