This work investigates the intrinsic characteristics of multilayer WSe field effect transistors (FETs) by analysing Pulsed - (PIV) and DC characteristics measured at various temperatures. In DC measurement, unwanted charge trapping due to the gate bias stress results in - curves different from the intrinsic characteristic. However, PIV reduces the effect of gate bias stress so that intrinsic characteristic of WSe FETs is obtained. The parameters such as hysteresis, field effect mobility (μ), subthreshold slope (), and threshold voltage () measured by PIV are significantly different from those obtained by DC measurement. In PIV results, the hysteresis is considerably reduced compared with DC measurement, because the charge trapping effect is significantly reduced. With increasing temperature, the field effect mobility (μ) and subthreshold swing () are deteriorated, and threshold voltage () decreases.
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| http://www.ncbi.nlm.nih.gov/pmc/articles/PMC5271170 | PMC |
| http://dx.doi.org/10.1186/s40580-016-0091-9 | DOI Listing |
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