Electrical Characteristics of Metal-Oxide-Semiconductor Capacitor with High-κ/Metal Gate Using Oxygen Scavenging Process.

It has been widely accepted that the mismatch of lattice constants between HfO2 and Si generates interface traps at the HfO2-Si interface, which causes the degradation of device performances. For better interface quality, very thin SiO2 film (< 2 nm) has been inserted as an interlayer (IL) between HfO2 and Si despite of the increase of EOT. In order to obtain both the better interface quality and the reduction of EOT, we used Ti metal on HfO2/IL SiO2 stack as a scavenging layer to absorb oxygens in the SiO2 and various annealing conditions were applied to optimize the thickness of the SiO2. As a result, we can effectively shrink the EOT from 3.55 nm to 1.15 nm while maintaining the same physical thickness of gate stacks. Furthermore, the diffusion of oxygen was confirmed by high resolution transmission electron microscopy (HRTEM) and time-of-flight secondary ion mass Spectrometry (SIMS).