Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaOx) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 10(6) cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing.
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Philos Trans A Math Phys Eng Sci
January 2025
Peter Gruenberg Institut (PGI-7), Forschungszentrum Juelich GmbH, Juelich, Germany.
The thirst for more efficient computational paradigms has reignited interest in computation in memory (CIM), a burgeoning topic that pivots on the strengths of more versatile logic systems. Surging ahead in this innovative milieu, multi-valued logic systems have been identified as possessing the potential to amplify storage density and computation efficacy. Notably, ternary logic has attracted widespread research owing to its relatively lower computational and storage complexity, offering a promising alternative to the traditional binary logic computation.
View Article and Find Full Text PDFNat Commun
September 2023
School of Microelectronics, Southern University of Science and Technology, 518055, Shenzhen, China.
The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µ /µ) of 85/140 cm/V·s is presented here.
View Article and Find Full Text PDFSci Rep
September 2023
University at Albany, College of Nanotechnology, Science and Engineering, Albany, NY, 12203, USA.
Analog hardware-based training provides a promising solution to developing state-of-the-art power-hungry artificial intelligence models. Non-volatile memory hardware such as resistive random access memory (RRAM) has the potential to provide a low power alternative. The training accuracy of analog hardware depends on RRAM switching properties including the number of discrete conductance states and conductance variability.
View Article and Find Full Text PDFAdv Mater
May 2024
School of Integrated Circuits, Beijing Advanced Innovation Center for Integrated Circuits, Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing, 100084, China.
ACS Appl Mater Interfaces
April 2023
Department of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden.
Memristors implemented as resistive random-access memories (RRAMs) owing to their low power consumption, scalability, and speed are promising candidates for in-memory computing and neuromorphic applications. Moreover, a vertical 3D implementation of RRAMs enables high-density crossbar arrays at a minimal footprint. Co-integrated III-V vertical gate-all-around MOSFET selectors in a one-transistor-one-resistor (1T1R) configuration have recently been demonstrated where an interlayer (IL)-oxide has been shown to enable high RRAM endurance needed for applications like machine learning.
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