Cognitive development is influenced by maturational changes in processing speed, a construct reflecting the rapidity of executing cognitive operations. Although cognitive ability and processing speed are linked to spindles and sigma power in the sleep electroencephalogram (EEG), little is known about such associations in early childhood, a time of major neuronal refinement. We calculated EEG power for slow (10-13 Hz) and fast (13.25-17 Hz) sigma power from all-night high-density electroencephalography (EEG) in a cross-sectional sample of healthy preschool children (n = 10, 4.3 ± 1.0 years). Processing speed was assessed as simple reaction time. On average, reaction time was 1409 ± 251 ms; slow sigma power was 4.0 ± 1.5 μV²; and fast sigma power was 0.9 ± 0.2 μV². Both slow and fast sigma power predominated over central areas. Only slow sigma power was correlated with processing speed in a large parietal electrode cluster (p < 0.05, r ranging from -0.6 to -0.8), such that greater power predicted faster reaction time. Our findings indicate regional correlates between sigma power and processing speed that are specific to early childhood and provide novel insights into the neurobiological features of the EEG that may underlie developing cognitive abilities.
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http://dx.doi.org/10.3390/brainsci5040494 | DOI Listing |
J Hazard Mater
January 2025
Department of Nuclear Science and Technology, School of Energy and Power Engineering, Xi'an Jiaotong University, Xi'an 710049, China.
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View Article and Find Full Text PDFTurk Arch Pediatr
January 2025
Department of Biostatistics, Lokman Hekim University Faculty of Medicine, Ankara, Türkiye.
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View Article and Find Full Text PDFSensors (Basel)
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Electronics Technology Department, University of Madrid Carlos III, 28911 Leganes, Spain.
This paper explores the implementation of a VCO-based ADC, achieving an ENOB of 12 bits with 1 MHz of a sampling rate in the audio bandwidth. The solution exploits the scalability and PVT invariance of a novel digital-to-frequency converter to reduce the size and consumed power. The architecture has been validated in a 130 nm CMOS technology node displaying a power consumption of 105.
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