Two-dimensional layered materials, such as transition metal dichalcogenides (TMDCs), are promising materials for future electronics owing to their unique electronic properties. With the presence of a band gap, atomically thin gate defined quantum dots (QDs) can be achieved on TMDCs. Herein, standard semiconductor fabrication techniques are used to demonstrate quantum confined structures on WSe2 with tunnel barriers defined by electric fields, therefore eliminating the edge states induced by etching steps, which commonly appear in gapless graphene QDs. Over 40 consecutive Coulomb diamonds with a charging energy of approximately 2 meV were observed, showing the formation of a QD, which is consistent with the simulations. The size of the QD could be tuned over a factor of 2 by changing the voltages applied to the top gates. These results shed light on a way to obtain smaller quantum dots on TMDCs with the same top gate geometry compared to traditional GaAs/AlGaAs heterostructures with further research.
Download full-text PDF |
Source |
|---|---|
| http://dx.doi.org/10.1039/c5nr04961j | DOI Listing |
Publication Analysis
Top Keywords
Similar Publications
A ferroelectrically modulated ultrasensitive two-dimensional perovskite phototransistor with zero-gate-bias.
Nanoscale
January 2025
State Key Laboratory of Electrical Insulation and Power Equipment, Xi'an Jiaotong University, Xi'an, 710049, China.
Two-dimensional (2D) organic-inorganic halide perovskites are promising sensitive materials for optoelectronic applications due to their strong light-matter interactions, layered structure, long carrier lifetime and diffusion length. However, a high gate bias is indispensable for perovskite-based phototransistors to optimize detection performances, since ion migration seriously screens the gate electric field and the deposition process introduces intrinsic defects, which induces severe leakages and large power dissipation. In this work, an ultrasensitive phototransistor based on the (PEA)SnI perovskite and the Al:HfO ferroelectric layer is meticulously studied, working without an external gate voltage.
View Article and Find Full Text PDFITZO-Based Self-Aligned Top Gate Thin-Film Transistor with Minimum Parasitic Capacitance for Long-Retention 2T0C DRAM.
ACS Omega
January 2025
School of Integrated Technology, Yonsei University, Seoul 03722, Republic of Korea.
We developed a two-transistor, zero-capacitor (2T0C) gain-cell memory featuring a self-aligned top-gate-structured thin-film transistor (TFT) for the first time. The proposed indium tin zinc oxide (ITZO) channel-incorporated architecture was specifically engineered to minimize parasitic capacitance for achieving long-retention 2T0C memory operations. A typical 2T0C structure features five types of parasitic capacitances; however, the proposed SATG design effectively used an essential gate insulator capacitance ( ) and reduced four nonessential capacitances ( , , , and ) to virtually zero.
View Article and Find Full Text PDFHardware-efficient preparation of architecture-specific graph states on near-term quantum computers.
Sci Rep
January 2025
Center for Integrated Quantum Science and Technology (IQST), University of Stuttgart, 70569, Stuttgart, Germany.
Highly entangled quantum states are an ingredient in numerous applications in quantum computing. However, preparing these highly entangled quantum states on currently available quantum computers at high fidelity is limited by ubiquitous errors. Besides improving the underlying technology of a quantum computer, the scale and fidelity of these entangled states in near-term quantum computers can be improved by specialized compilation methods.
View Article and Find Full Text PDFPatient specific variables impact sensitivity to association between joint balance and 2 Year outcomes.
J Orthop
July 2025
Department of Orthopaedic Surgery, Rush University Medical Center, Il, USA.
Background: This study investigates the association between intra-operative balance and 2-year outcomes within subgroups defined by demographics and pre-operative joint balance. Our hypothesis is that patient demographics and the pre-operative state of the joint will impact patient sensitivity to post-operative balance and laxity and subsequent impact on outcome.
Methods: A retrospective analysis of prospectively captured data across 5 sites with 5 surgeons was performed.
Parallelized Field-Programmable Gate Array Data Processing for High-Throughput Pulsed-Radar Systems.
Sensors (Basel)
January 2025
Computer-Aided Design and Test (CADT) Research Group, McMaster University, Hamilton, ON L8S 4L8, Canada.
A parallelized field-programmable gate array (FPGA) architecture is proposed to realize an ultra-fast, compact, and low-cost dual-channel ultra-wideband (UWB) pulsed-radar system. This approach resolves the main shortcoming of current FPGA-based radars, namely their low processing throughput, which leads to a significant loss of data provided by the radar receiver. The architecture is integrated with an in-house UWB pulsed radar operating at a sampling rate of 20 gigasamples per second (GSa/s).
View Article and Find Full Text PDFWant AI Summaries of new PubMed Abstracts delivered to your In-box?
Enter search terms and have AI summaries delivered each week - change queries or unsubscribe any time!