We report a low-temperature InP p-MOS with a high capacitance density of 2.7 µF/cm2, low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.
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| http://dx.doi.org/10.1166/jnn.2015.9208 | DOI Listing |
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