This work presents a novel hardware phase-unwrapping architecture for digital holographic microscopy. The architecture is based on an iterative region-referenced algorithm because of its simplicity and effectiveness for phase unwrapping. The architecture therefore consumes fewer hardware resources for very large-scale integration implementation. In addition, a novel data reuse scheme is adopted for reducing the memory bandwidth required by the architecture. The architecture can then have fast computation speed for the iterative operations. The architecture has been implemented by field programmable gate array. It acts as a hardware accelerator in an embedded system developed by a network-on-chip platform for performance measurement. The superiorities of the proposed architecture have been confirmed by the experiments.
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