The ability to incorporate rigid but high-performance nanoscale nonplanar complementary metal-oxide semiconductor (CMOS) electronics with curvilinear, irregular, or asymmetric shapes and surfaces is an arduous but timely challenge in enabling the production of wearable electronics with an in situ information-processing ability in the digital world. Therefore, we are demonstrating a soft-material enabled double-transfer-based process to integrate flexible, silicon-based, nanoscale, nonplanar, fin-shaped field effect transistors (FinFETs) and planar metal-oxide-semiconductor field effect transistors (MOSFETs) on various asymmetric surfaces to study their compatibility and enhanced applicability in various emerging fields. FinFET devices feature sub-20 nm dimensions and state-of-the-art, high-κ/metal gate stacks, showing no performance alteration after the transfer process. A further analysis of the transferred MOSFET devices, featuring 1 μm gate length, exhibits an ION value of nearly 70 μA/μm (VDS = 2 V, VGS = 2 V) and a low subthreshold swing of around 90 mV/dec, proving that a soft interfacial material can act both as a strong adhesion/interposing layer between devices and final substrate as well as a means to reduce strain, which ultimately helps maintain the device's performance with insignificant deterioration even at a high bending state.
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http://dx.doi.org/10.1021/acsnano.5b00686 | DOI Listing |
Nano Lett
January 2025
Key Lab for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China.
One-time programmable (OTP) memory is an essential component in chips, which has extremely high security to protect the stored critical information from being altered. However, traditional OTP memory based on the thermal breakdown of the dielectric has a large programming current, which leads to high power consumption. Here, we report a gate tunneling-induced "cold" breakdown phenomenon in carbon nanotube (CNT) field-effect transistors, and based on this we construct a "cold" fuse (C-fuse) memory where applying a mild gate voltage can break down the CNT channel without damaging the gate dielectric.
View Article and Find Full Text PDFNano Lett
January 2025
Hunan Provincial Key Laboratory of Two-Dimensional Materials, State Key Laboratory for Chemo/Biosensing and Chemometrics, College of Chemistry and Chemical Engineering, Hunan University, Changsha 410082, China.
Two-dimensional (2D) transition metal dichalcogenides (TMDs), such as WSe, are promising candidates for next-generation integrated circuits. However, the dependence of intrinsic properties of TMD devices on various processing steps remains largely unexplored. Here, using pristine p-type WSe devices as references, we comprehensively studied the influence of each step in traditional nanofabrication methods on device performance.
View Article and Find Full Text PDFAnal Chem
January 2025
State Key Laboratory of Biogeology and Environmental Geology, Engineering Research Center of Nano-Geomaterials of the Ministry of Education, Faculty of Materials Science and Chemistry, China University of Geosciences, Wuhan 430074, P. R. China.
Proteins have been one of the most important biomarkers for diagnosing diseases, and field-effect transistor (FET) biosensors possess high sensitivity; are label-free; and feature real-time detection, rapidity, and easy integration for protein detection. FET biosensors are mainly made up of FET parts, such as channel materials, and bio parts, such as receptors. This Tutorial provides an in-depth exploration of FET biosensors for protein detection from the composition perspective and discusses the commercialization of point-of-care diagnostics of proteins based on FET biosensors.
View Article and Find Full Text PDFNano Lett
January 2025
Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-41296 Göteborg, Sweden.
Semiconducting transition metal dichalcogenides (TMDs) have attracted significant attention for their potential to develop high-performance, energy-efficient, and nanoscale electronic devices. Despite notable advancements in scaling down the gate and channel length of TMD field-effect transistors (FETs), the fabrication of sub-30 nm narrow channels and devices with atomic-scale edge control still poses challenges. Here, we demonstrate a crystallography-controlled nanostructuring technique to fabricate ultranarrow tungsten disulfide (WS) nanoribbons as small as sub-10 nm in width.
View Article and Find Full Text PDFAdv Mater
January 2025
Department of Materials Science and Metallurgy, University of Cambridge, Cambridge, CB3 0FS, UK.
Thick metamorphic buffers are considered indispensable for III-V semiconductor heteroepitaxy on large lattice and thermal-expansion mismatched silicon substrates. However, III-nitride buffers in conventional GaN-on-Si high electron mobility transistors (HEMT) impose a substantial thermal resistance, deteriorating device efficiency and lifetime by throttling heat extraction. To circumvent this, a systematic methodology for the direct growth of GaN after the AlN nucleation layer on six-inch silicon substrates is demonstrated using metal-organic vapor phase epitaxy (MOVPE).
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