A stacked oxide semiconductor of n-type ZnO/p-type NiO with diode behavior was proposed as the novel charge-trapping layer to enable low-voltage flash memory for green electronics. The memory performance outperforms that of other devices with high κ and a nanocrystal-based charge-trapping layer in terms of a large hysteresis memory window of 2.02 V with ±3 V program/erase voltage, a high operation speed of 1.88 V threshold voltage shift by erasing at -4 V for 1 ms, negligible memory window degradation up to 10(5) operation cycles, and 16.2% charge loss after 10 years of operation at 85 °C. The promising electrical characteristics can be explained by the negative conduction band offset with respect to Si of ZnO that is beneficial to electron injection and storage, the large number of trapping sites of NiO that act as other good storage media, and most importantly the built-in electric field between n-type ZnO and p-type NiO that provides a favorable electric field for program and erase operation. The process of diode-based flash memory is fully compatible with incumbent VLSI technology, and utilization of the built-in electric field ushers in a new avenue of accomplishing green flash memory.
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http://dx.doi.org/10.1021/am507535c | DOI Listing |
Micromachines (Basel)
December 2024
Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, 20133 Milan, Italy.
Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase.
View Article and Find Full Text PDFMicromachines (Basel)
November 2024
School of Computer and Artificial Intelligence, Wuhan University of Technology, Wuhan 430070, China.
With vertical stacking, 3D NAND's flash memory can achieve continuous capacity growth. However, the endurance variation between the stacked layers becomes more and more significant due to process variation, which will lead to the underutilization of many pages and seriously affect the lifetime of 3D NAND's flash memory. We investigated the endurance variation characteristics between layers and divided the stacked layers into the top, middle, and bottom layers according to the endurance characteristics.
View Article and Find Full Text PDFJ Magn Reson
January 2025
Bridge12 Magnetic Resonance, 11 Michigan Drive, Natick, MA 01760, USA. Electronic address:
We present a fully automated cryogenic sample insertion and ejection system for use with low-temperature EPR probes. We show how the system can be implemented on a conventional EPR spectrometer and that ejection and insertion is reliably possible at temperatures down to 10 K. Furthermore, we investigate the glass properties of a 0.
View Article and Find Full Text PDFConscious Cogn
January 2025
Department of Experimental Psychology, Helmholtz Institute, Utrecht University, Utrecht, the Netherlands.
Items held in visual working memory (VWM) influence early visual processing by enhancing memory-matching visual input. Depending on current task demands, memory items can have different priority states. Here, we investigated how the priority state of items in VWM affects two key aspects of early visual processing: access to visual awareness and attention allocation.
View Article and Find Full Text PDFHeliyon
March 2024
Electrical-Electronics Engineering, Istanbul University-Cerrahpasa, Istanbul 34320, Turkey.
We propose a new bootloader design with dynamic boot addressing to increase the endurance of microcontroller flash memories and to use flash memory efficiently. Although the final industrial products are not updated much, regular programming during the development and testing phase inefficiently reduces the endurance of flash memory. Especially after the pandemic, the problems experienced in the production/supply processes of products using semiconductor technology and the highly extended deadlines have inspired our work to extend the life of the products used in the development and testing phase.
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