Integration of SrTiO3 on crystallographically oriented epitaxial germanium for low-power device applications.

ACS Appl Mater Interfaces

Advanced Devices & Sustainable Energy Laboratory (ADSEL), Bradley Department of Electrical and Computer Engineering, Virginia Tech , Blacksburg, Virginia 24061, United States.

Published: March 2015

SrTiO3 integration on crystallographic oriented (100), (110), and (111) epitaxial germanium (Ge) exhibits a potential for a new class of nanoscale transistors. Germanium is attractive due to its superior transport properties while SrTiO3 (STO) is promising due to its high relative permittivity, both being critical parameters for next-generation low-voltage and low-leakage metal-oxide semiconductor field-effect transistors. The sharp heterointerface between STO and each crystallographically oriented Ge layer, studied by cross-sectional transmission electron microscopy, as well as band offset parameters at each heterojunction offers a significant advancement for designing a new generation of ferroelectric-germanium based multifunctional devices. Moreover, STO, when used as an interlayer between metal and n-type (4 × 10(18) cm(-3)) epitaxial Ge in metal-insulator-semiconductor (MIS) structures, showed a 1000 times increase in current density as well as a decrease in specific contact resistance. Furthermore, the inclusion of STO on n-Ge demonstrated the first experimental findings of the MIS behavior of STO on n-Ge.

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http://dx.doi.org/10.1021/am5091726DOI Listing

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